The present application relates to a memory apparatus and a memory control method for controlling the memory apparatus that may include a nonvolatile memory used illustratively as a flash memory.
Memory apparatus equipped with a flash memory has existed typically for use as an external storage to such devices as personal computers, digital still cameras, digital video cameras, and audio recorders. Data is usually written to and read from the flash memory in units of clusters on a random basis, whereas data is deleted from the flash memory generally in units of blocks.
In the flash memory, memory elements degrade through repeated data updates and are thus subject to constraints on the number of updates. Measures are taken to prevent repeated access to particular clusters in order to maximize the service life of the flash memory. More specifically, when data having a logical address corresponding to a given physical address is to be updated, the new data will be written not to the same physical block but to a new, unused physical block (free block) instead.
Before and after a data update, the same logical address is assigned to different physical addresses. For this reason, the flash memory is arranged to hold an address conversion table specifying the relations of correspondence between the logical and physical addresses in use. When the memory apparatus is attached to a host apparatus, the address conversion table is retrieved from the flash memory and loaded into a working memory of the host or memory apparatus.
In the typical memory apparatus, an update of data in only a few sectors still leads to the update of an entire physical block. It takes time to accomplish the access involved with the update, which would promote memory element degradation. The update-incurred access is minimized illustratively by dividing each of the blocks in the flash memory into a header area and a data area. A data record to be written to the data area has its start address and its record length written to the header area. Each data record to be written to the data area is supplemented by a link information area and a flag area. Data is thus written and updated in units of data records. When there is no available space left in a given block, effective data records are extracted from the block and transferred to a free block; the initial block from which the transfer was effected is deleted (e.g., see Japanese Patent Laid-Open No. Hei 11-73363).
One disadvantage of the typical flash memory in which each block is divided into the header and data areas is the failure to use the memory effectively. Because each block is furnished with a header area, a link information area and a flag area, the capacity of the memory to accommodate data tends to drop.
One way to bypass the disadvantage above has been proposed by this applicant in the form of a memory apparatus, a memory apparatus control method, and a data processing system disclosed in Japanese Patent Application No. 2005-225716. The inventive arrangements involve establishing a logical to physical conversion table that specifies the correspondence between logical and physical block addresses together with the ending cluster number of each physical block. In operation, a check is made to determine whether the starting cluster number SC of the data to be written based on a write instruction is larger than the ending cluster number EC of a given physical block in the logical to physical conversion table. If the starting cluster number SC is found larger than the ending cluster number EC, the data is added to the physical block with no physical block update carried out as in usual cases (where the new data would be written and the original physical block copied).
The arrangements proposed above help reduce the frequency of flash memory deletion and efficiently update data in the flash memory without significantly reducing its storage capacity. Degradation of the memory elements is thus lowered while the speed of access to data locations is enhanced.
According to the above-cited Patent Application, the memory apparatus furnished with a nonvolatile memory as its recording medium is kept from overwriting the nonvolatile memory with data. Furthermore, the increments in which to write and to delete data differ between these two operations (i.e., data is handled in smaller units when written than when deleted). Data may be added into blocks of the nonvolatile memory.
A memory apparatus using an FAT (file allocation tables) file system usually needs management information updates in the FAT as well as directory entry updates at the same time that file data is written.
A recording apparatus that retains management information has a memory area in which to hold the management information in addition to the data area for use by the user. Every time a host writes file data, the recording apparatus updates the management information in its flash memory.
A memory apparatus having a cache block arrangement holds data in units of clusters in the cache block. The relations of correspondence between logical and physical addresses in the cache block are fixed (i.e., logical addresses are assigned in ascending order starting from the beginning of the physical block).
The above arrangements, because of their constitution, let a write-back take place during a write of file data to continuous logical addresses in excess of a designated logical boundary representative of a logical space size in a plurality of sectors, even if the update size is less than the cluster size. The write-back process entails block deletion, which will result in a shortened service life of the product. Another disadvantage is that the write-back incurs a decrease in write performance due to the garbage collection and deletion involved.
At the time of management information updates in the FAT and directory entry updates in conjunction with file data writes, overwrite operations occur frequently because access is concentrated on particular logical addresses. This is attributable to the fact that the size of the files to be written is short of the designated logical boundary representing the logical space size in units of a plurality of sectors. In the case of the above-mentioned arrangements proposed by this applicant, whenever a write is made to the logical space from which data has been written to a cache block, a write-back takes place. The write-back process entails block deletion leading to a shortened service life of the product. The write-back further incurs a drop in write performance attributable to garbage collection and deletion.
That is, because the nonvolatile memory (NAND type flash memory) cannot be overwritten with data and because data is deleted in units of blocks, the memory apparatus typically needs to keep the logical to physical conversion table consistent in terms of what is contained therein. For this reason, the write-back process entails saving the update data into another block on a block by block basis regardless of the size of the update data. Any data other than the update data in the original block needs to be copied through garbage collection. Since there emerges a block containing unnecessary data following the update, that block needs to be deleted. However, there exist constraints on the number of times blocks can be deleted.